1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, more particularly to a timing-control circuit and a clock distribution system which can generate and transmit or distribute a synchronous signal.
2. Description of the Related Art
Conventionally, a phase-locked loop (PLL) has been used for a semiconductor integrated circuit which handles a clock signal. The PLL circuit, as shown in FIG. 45, comprises a phase frequency detector 280, a loop filter 281, and a voltage controlled oscillator 282. The PLL circuit detects a phase difference between the reference clock signal clkref 271 and the inner clock signal 277 entered to the phase frequency detector 280 and outputs a clock error signal clkerr 272. The loop filter 281 rectifies the clock error signal clkerr 272 to a DC voltage and outputs the voltage as a control signal cntsig 273. The voltage controlled oscillator 282 generates an output clock signal clkout 276, which has a frequency determined by the voltage of the control signal cntsig 273. The output clock signal clkout 276 is supplied to the phase frequency detector 280 as an inner clock signal clkin 277. The phase frequency detector 280 stops the output if no difference is detected between input signals, thereby the PLL operation is stabilized. At this time, the reference clock signal clkref 271 and the output clock signal clkout 276 are synchronized with each other in phase. The PLL circuit takes a long time (several xcexcm sec) until the output clock signal clkout 276 generation is stabilized. Usually, when the subject system stands by, the PLL operation is stopped, thereby saving the power consumption.
However, the PLL circuit has a problem that the circuits needs a long settling time before it is restarted. In order to avoid such a long settling time, therefore, some systems are provided with a sleep mode respectively, which avoids stopping the PLL circuit even at the stand-by time. The PLL circuit thus consumes the power at its stand-by time.
The official gazette of Japanese Patent Laid-Open No. 8-237091 has disclosed a synchronous mirror delay circuit for solving the disadvantages peculiar to such the PLL circuit. This synchronous mirror delay circuit does not multiply a frequency of any input clock signal. The circuit is dedicated just for phase synchronization. When compared with the PLL circuit, its power consumption is lower and its circuit size is smaller.
FIG. 44 shows a configuration of such a synchronous mirror delay circuit. The synchronous mirror delay circuit 260 comprises a forward delay array 261, a backward delay array 263, and a delay detect circuit 262. The input clock signal clkin 251, passing the replica of buffer 264 having a delay time of Tbuf2, becomes a delayed clock signal clkbuf 252, then entered to the forward delay array 261. The forward delay array 261 outputs a plurality of clock signals, each having a different delay time from the delayed clock signal clkbuf 252. The clock signals are transmitted to the delay detect circuit 262. Some of those signals from the forward delay array 261 have a delay time of (Tclkxe2x88x92Tbuf2). The delay detect circuit 262 detects the output positions of those (tclkxe2x88x92Tbuf2) signals using the input clock signal clkin 251 as a control signal. The Tclk indicates an cycle time of the input clock signal clkin 251. The Tbuf2 indicates an operation delay time of the replica of buffer 264. The delay detect circuit 262 transfers the detected signal to the backward delay array 263. The clock signal is transmitted in the reverse direction of the forward delay array 261 from the detected position in the backward delay array 263, so as to output a clock signal clksmd 253. The clock signal clksmd 253 has a delay time of (Tclkxe2x88x92Tbuf2) from the input clock signal clkin 251. The clock signal clksmd 253 from the synchronous mirror delay circuit is distributed to a predetermined circuit as a distribution clock signal clkout 254 at the clock buffer 265. If the delay time of the clock buffer 265 is Tbuf1, the delay time difference (Tdel1) between the input clock signal clkin 251 and the distribution clock signal clkout 254 becomes (Tclkxe2x88x92Tbuf2+Tbuf1). If the delay time difference Tbuf1 is the same between the replica of buffer 264 and the clock buffer 265, the delay time difference between them becomes Tdel=Tclk. A signal synchronized with the input clock signal can thus be supplied as a distribution clock signal. This distribution clock signal can be settled within several clock cycles after the operation is started.
In order to equalize both delay times (Tbuf2 of the replica of buffer 264 and Tbuf1 of the clock buffer 265) as shown in FIG. 44, the replica of buffer 264 shouldbe designed according to the clock buffer 265. If the load of the clock buffer 265 is unknown or if the load of the clock buffer 265 is changed after the circuit is designed or if the load 266 is unknown or undefined, therefore, the replica of buffer 264 cannot compensate the delay time at this portion. In addition, no synchronous signal can be generated when the delay time of the clock buffer 265 is changed due to a change of the circuit characteristics caused by a manufacturing process and a temperature change during an operation.
The technique for considering changes of a load in the synchronous mirror delay circuit is described in xe2x80x9cThe Direct Detect Synchronous Mirror Delay (Direct SMD) for ASICsxe2x80x9d IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp511-514, 1998. In other words, the synchronous mirror delay circuit is not provided with any feed-back circuit, but provided two delay lines and one replica of delay circuit. The clock driver dummy circuit is omitted in the replica of delay circuit and a feed-back circuit is employed instead of the dummy circuit. However, the document does not describe any concrete configuration of the synchronous mirror delay circuit. In addition, the synchronous mirror delay circuit can obtain output clock signals whose duty ratio is only 1/10 or so respectively. This is why the circuit cannot be employed for a system which uses both rising and falling of each clock signal.
Under such the circumstances, it is an object of the present invention to solve the problems of the conventional synchronous mirror delay circuit described above and provide a timing-control circuit device and a clock distribution system which can correspond to changes of an output load. More concretely, it is an object of the present invention to provide a timing-control circuit device and a clock distribution system which can supply a clock distribution signal kept synchronized in phase with an input clock signal even when the delay time of the clock signal is changed due to such a load as a clock buffer. The timing-control circuit device uses a synchronous mirror delay circuit.
Hereunder, some representative inventions disclosed in this specification will be described briefly.
The timing-control circuit (SMDF 14) of the present invention receives such a first transfer signal (clkin 11) as a reference clock signal, etc., thereby generating such a second transfer signal (clk 12) as an internal clock, and further generating such a third transfer signal (clkout 13) as an external clock, etc. through a buffer (BUF 15). At this time, the timing-control circuit (SMDF 14) receives a fed-back external clock signal, thereby generating an internal clock signal so as to establish the synchronization of phase between the external clock signal and the reference clock signal. Inside the timing-control circuit (SMDF 14) are provided circuits (FDA 21, MCC 22, and REG 23) for detecting a phase difference between internal clock and external clock, as well as a delay circuit (DCL 24) for controlling the delay time. The delay circuit can change the delay time according to the detected phase difference. Consequently, the same phase can be assumed between external and internal clock signals.
According to the means described above, the settling time within which a clock output is stabilized is such short. For example, therefore, the timing-control circuit can be started only when a clock is needed in the object semiconductor circuit device, thereby saving the power consumption, as well as suppressing degradation of the accuracy of an output signal, which is caused by a drop of the supply voltage. Since the fast settling characteristics of the synchronous mirror delay circuit are kept as are such way, the present invention can cope easily with load changes of a clock output in a load.
Hereunder, the present invention will be described more in detail. The timing-control circuit device is provided with a logic circuit (SMDF 14) for receiving the first transfer signal (clkin 11) and outputting the second transfer signal (dclk 12) and a load circuit (BUF 15, LD 16) for receiving the second transfer signal and outputting the third transfer signal (clkout 13). The logic circuit receives the fed-back third transfer signal, thereby generating the second transfer signal so as to synchronize the phase of the first transfer signal with the phase of the third transfer signal. The logic circuit comprises a first delay circuit array (FDA 21, MCC 22, and REG 23) for generating a control signal according to the phase difference and a second delay circuit array (DCL 24) which can change the delay time of the third transfer signal with respect to the first transfer signal according to a control signal.
The first delay circuit array comprises a forward delay circuit (FDA 21) for enabling a delayed signal from a plurality of positions respectively while transferring the third transfer signal with a little delay in one direction, and a detecting circuit (MCC 22) for generating a plurality of control signals (mcout) according to the phase difference between each delayed signal output from the forward delay circuit and the second transfer signal, so that any of generated control signals, which are regarded not to have a phase difference, indicates the output position of the delayed signal corresponding to itself so as to be distinguished from other output positions. The second delay circuit array (DCL 24) receives the plural control signals and gives a delay time to the first transfer signal corresponding to the delay time of the third transfer signal in a section up to the output position distinguished from other output positions in the forward delay circuit according to the control signal, thereby generating the second transfer signal.
In the above configuration, the timing-control circuit device can further be provided with a register (REG 23), which latches a control signal output from the control circuit synchronously with the second transfer signal and supplies the latched control signal to the second delay circuit array. At this time, the cycle of the second transfer signal is used to update the cycle of the control signal. In this case, however, a malfunction might occur between the detection timing of the detecting circuit (MCC 22) and the timing for latching the control signal by the register (REG 23). In order to avoid such a malfunction, therefore, the updating cycle (latching cycle) of the control signal in the storing circuit should be set longer. And for this purpose, the timing-control circuit device can further be provided with a divider (DFF 61) for receiving the second transfer signal (dclk 12) and outputting a divided signal; a buffer (BUF 65) for giving a delay time to the output signal from the divider, and another register (REG 23) for latching the control signal output from the control circuit synchronously with the cycle of the signal output from the buffer, then supplying the latched control signal to the second delay circuit array.
An operation delay can be reduced by reducing an input load capacity component recognizable from the second transfer signal. In order to achieve this reduction of such an operation delay, the first to third signal distribution circuits (BUFT 41, 42, and 43) should be employed, thereby branching an input signal in a plurality of buffers so that a distribution signal is supplied to each of the plural output terminals. At this time, the first signal distribution circuit is composed so as to receive the first transfer signal and output a distribution signal to the second delay circuit array (DCL 24), the second signal distribution circuit is composed so as to receive the second transfer signal and output a distribution signal to the control circuit (MCC 22), and the third signal distribution circuit is composed so as to receive the second transfer signal and output a distribution signal to the storing circuit (REG 23).
Gnerally, the state of the control signal is not stabilized while the phase of the third transfer signal is not synchronized with the phase of the first transfer signal. Such an unstable state must be prevented in order to stabilize the operation of a circuit. One of measures to be taken to prevent such a problem is employing the following configuration for the timing-control circuit device. At first, the timing-control circuit device is provided with a gate circuit (NOR 51) so that the plural control signals are set on the first level while the phase of the third transfer signal is not synchronized with the phase of the first transfer signal, and the control signals are then set on the second level when the above phase synchronization is established. And, when all the control signals are set on the first level, a pseudo control signal is generated on the second level, so that at least one control signal is set on the second level and the pseudo control signal is set on the first level. The second delay circuit array can also be composed so as to receive the pseudo signal and output the first transfer signal to a predetermined circuit as the second transfer signal according to the second level of the pseudo control signal.
The load circuit, as shown in FIG. 22, can branch the second transfer signal in a plurality of buffers, so that a branched signal is dispersed into those loads. A signal distributed to a load is assumed to become the third transfer signal at this time.
And furthermore, the timing-control circuit device is provided with a coarse timing-control circuit and a fine timing-control circuit. The coarse timing-control circuit synchronizes the phase of an output signal with the phase of a reference clock signal at a low accuracy, then the fine timing-control circuit synchronizes the phase of the output clock signal with the phase of the reference clock signal at a high accuracy. The size of a skew to be generated in an output clock signal is decided by the delay element in the fine timing-control circuit. The skew can be reduced by reducing the delay time per delay element stage in the fine timing-control circuit. The scale of the timing-control circuit can be adjusted freely by a delay time ratio between the delay element in the coarse timing-control circuit and the delay time in the fine timing-control circuit. The use of an optimized ratio will thus reduce the size, area, and power consumption of the circuit.
The clock distribution system, as shown in FIG. 23, comprises a semiconductor integrated circuit (LSI 81) provided with a timing-control circuit (SMDF 14); a clock generator (CPG 82); andaclockdistributor (CDB 83); aswell as a load connected to the semiconductor integrated circuit. The clock generator has a plurality of internal loads (LD 84), each of which is operated synchronously with the first clock signal (clkin 11) and the clock distribution circuit generates the fourth clock signal (clk 85) obtained by branching the fourth clock signal in a plurality of buffers. The timing-control circuit receives the first clock signal (clkin 11) and the third clock signal (clkfb 86) and outputs the second clock signal (clkout 13). The second clock signal is output outside the semiconductor integrated circuit and fed back as the third clock signal through a load. The fed-back third clock signal is then used to generate the second clock signal, thereby synchronizing the phase of the first clock signal with the phase of the third clock signal. The timing-control circuit thus comes to comprise the first delaycircuit array for detecting aphase difference between the third clock signal and the second clock signal, thereby generating a control signal according to the detected phase difference; and the second delay circuit array, which can change the delay time of the third clock signal with respect to the first clock signal according to the control signal. Consequently, this configuration makes it possible to synchronize the clock signal (clkin 11) distributed in the semiconductor integrated circuit (LSI 81) with the clock signal (clkfb 86) distributed in the semiconductor integrated circuit (LSI 81) without using any external load.
As shown in FIG. 24, the second clock signal can be fed back directly to the timing-control circuit as the third clock signal in the semiconductor integrated circuit. If the signal is fed back so, one external terminal can be reduced from the semiconductor integrated circuit. In this case, however, it is expected that the follow-up property of the external load is a little more degraded than that of the above configuration of the timing-control circuit device.
Another clock distribution system, as shown in FIG. 25, includes the first semiconductor integrated circuit (LSI 91) provided with a timing-control circuit (SMDF 14); and the second semiconductor integrated circuits (LSI 92 to 94) operated synchronously with a clock signal respectively. The timing-control circuit receives the first clock signal (clkin 11) generated in the first semiconductor integrated circuit and the third clock signal (clkfb 95) supplied from outside the first semiconductor integrated circuit and outputs the second clock signal (clkout 13). The second clock signal is supplied to and fed back from the first semiconductor integrated circuit as the third clock signal. The fed-back third clock signal is used to generate the second clock signal so as to synchronize the phase of the first clock signal with the phase of the third clock signal. The timing-control circuit thus comes to comprise the first delay circuit array for detecting a phase difference between the third clock signal and the second clock signal, thereby generating a control signal according to the detected phase difference; and the second delay circuit array, which can change the delay time of the third clock signal according to the control signal with respect to the first clock signal. Consequently, the present invention can provide a clock distribution system which can keep supplying of a clock signal (clkfb 95) synchronously with an internal clock signal (clkin 11) even when a clock signal is supplied outside the semiconductor integrated circuit (LSI 91). In addition, the clock distribution system can supply a synchronous signal even when a clock signal is supplied to external using a long distance cable.
These and other objects, features and advantages of the present invention will become more apparent in view of the following detailed description of the preferred embodiments in conjunction with accompanying drawings.